We held our next tinyML Talks webcast with two presentations: Ian Campbell from OnScale has presented Training Embedded AI/ML Using Synthetic Data and Weiwen Jiang from University of Notre Dame has presented Using AI to design energy-efficient AI accelerators for the edge on December 8, 2020 at 8:00 AM and 8:30 AM Pacific Time.
Ian Campbell (left) and Weiwen Jiang (right)
In the past, engineers relied on physical testing to generate datasets to train embedded AI and ML algorithms. Today, engineers at world-class companies are using Cloud Simulation to generate “synthetic” datasets for training embedded AI/ML. Cloud Simulation empowers engineers to run massive parametric sweeps of things like sensors within a system that are subjected to variances in manufacturing and environmental operating conditions. Simulation also allows engineers and data scientists to control noise within the AI/ML dataset - either removing it entirely for baseline analysis or injecting various types of noise (e.g. thermal or vibration noise) into a sensor system to ensure AI/ML algorithms are robust against noise.
Ian Campbell is a Georgia Tech trained engineer and serial entrepreneur, having founded two Silicon Valley high tech companies. The first, NextInput, broke records in getting a new MEMS technology to market in high volume applications like smartphones and wearables.
The second, OnScale, is a Cloud Engineering Simulation platform backed by Intel Capital and Google’s Gradient Ventures. OnScale Cloud combines advanced proprietary multiphysics solvers with cloud supercomputers and AI/ML and breaks performance and cost constraints for engineers optimizing Digital Prototypes of devices like next-gen MEMS, 5G RF filters, IoT devices, medical devices, and much more. OnScale massively reduces cost, risk, and time-to-market for R&D firms pushing the boundaries of new technology.
In this talk I will present a novel machine learning driven hardware and software co-exploration framework for overcoming the challenge of automating the design of energy-efficient hardware accelerators for neural networks. Different from existing hardware-aware neural architecture search (NAS) which assumes a fixed hardware design and explores the NAS space only, such a framework simultaneously explores both the architecture search space and the hardware design space to identify the best neural architecture and hardware pairs that maximize both accuracy and hardware efficiency metrics. Especially for running machine learning on resource constrained edge devices, such a practice greatly opens up the design freedom. We will see how we can significantly push forward the Pareto frontier between hardware efficiency and model accuracy for better design tradeoffs, and rapid time to market for flexible accelerators designed from the ground.
Dr. Weiwen Jiang is currently a Post-Doctoral Research Associate at the University of Notre Dame U.S… He received the Ph.D. degree from Chongqing University in 2019. From 2017 to 2019, he was a research scholar in the Department of Electrical and Computer Engineering at the University of Pittsburgh. His research interest is on Hardware and Software Co-Design; in particular, he proposed the first co-design framework to search for Neural Network Architectures and FPGA designs. Most recently, he moves into the research field of TinyML and successfully applies the co-design philosophy for ASIC and Computing-in-Memory accelerators. He is the receipt of Best Paper Award in ICCD’17 and Best Paper Nominations in DAC’19, CODES+ISSS’19, ASP-DAC’16, and ASP-DAC’20.
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