We held our next tinyML Talks webcast. Kaiyuan Yang from Rice University and Weier Wan from Aizip presented Processing-In-Memory for Efficient AI Inference at the Edge on October 13, 2022.
Performing ever-demanding AI tasks in battery powered edge devices requires continuous improvement in AI hardware energy and cost-efficiency. Processing-In-Memory (PIM) is an emerging computing paradigm for memory-centric computations like deep learning. It promises significant energy efficiency and computation density improvements over conventional digital architectures, by alleviating the data movement costs and exploiting ultra-efficient low-precision computation in the analog domain. In this talk, Dr. Kaiyuan Yang will share his research group’s recent silicon-proven SRAM-based PIM circuit and system designs, CAP-RAM and MC2-RAM. Next, Dr. Weier Wan will introduce his recent RRAM-based PIM chip, NeuRRAM. Through full-stack algorithm-hardware co-design, these demonstrated PIM systems attempt to alleviate the critical inference accuracy loss associated with PIM hardware while retaining the desired energy, memory, and chip area benefits of PIM computing.
Dr. Kaiyuan Yang is currently an Assistant Professor of ECE at Rice University, USA. He received his B.S. degree in Electronic Engineering from Tsinghua University, China, in 2012, and his Ph.D. degree in Electrical Engineering from the University of Michigan, Ann Arbor, in 2017. His research interests include digital and mixed-signal circuit and system design for secure and intelligent microsystems, bioelectronics, and hardware security. Dr. Yang is a recipient of the 2022 National Science Foundation (NSF) CAREER award, 2016 IEEE SSCS Predoctoral Achievement Award, and multiple best paper awards from premier conferences in various fields, including 2021 IEEE Custom Integrated Circuit Conference i(CICC), 2016 IEEE Symposium on Security and Privacy (Oakland), 2015 IEEE International Symposium on Circuits and Systems (ISCAS), and the Best Student Paper Award finalist at 2022 RFIC and 2019 CICC.
Dr. Weier Wan is currently leading the software-hardware co-design and is a founding member at Aizip, a Silicon Valley startup providing TinyML solutions. He received his Ph.D. degree in electrical engineering from Stanford University in 2022, where he worked on designing efficient AI hardware system to enable intelligence at the edge. His research work has been published in top journals and conferences, including Nature, International Solid-State Circuits Conference (ISSCC), and Symposium on VLSI Technology and Circuits. He is the first author of a monumental work published in Nature this year, titled “A compute-in-memory chip based on resistive random-access memory”. Previously, he received his master’s degree in electrical engineering from Stanford University in 2018 and his bachelor’s degree in physics, electrical engineering and computer sciences from University of California, Berkeley in 2015.
Watch on YouTube:
Kaiyuan Yang and Weier Wan
Download presentation slides:
Kaiyuan Yang and Weier Wan
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